How to hire VHDL and Verilog engineers in 2026: A sourcing guide

Hardware description languages are not programming languages. That distinction matters more than almost anything else in this guide. VHDL, Verilog, and SystemVerilog describe physical circuits. The code does not run sequentially on a processor. It synthesizes into logic gates, flip-flops, and interconnects that operate in parallel on silicon. An engineer who writes Verilog thinks about clock edges and timing constraints, not function calls and memory allocation. If you are hiring these engineers, knowing that difference will sharpen your outreach and your evaluations.

Until recently, chip design was almost entirely behind closed doors. Engineers wrote proprietary RTL for Intel, Qualcomm, and Broadcom on internal repositories that no recruiter could see. That is changing. The RISC-V movement, the CHIPS Alliance, and projects like OpenTitan and LiteX have brought real chip design work to GitHub. GitHub is now a viable sourcing channel for a talent pool that used to be invisible outside the semiconductor industry.

This guide covers where HDL engineers work, what separates a junior RTL designer from someone who can close timing on a 500 MHz FPGA, how the AI chip boom has changed compensation, and how to build a sourcing workflow for engineers who describe hardware for a living.

The HDL engineer market in 2026

The shortage is structural, not cyclical. There are roughly 20,000 to 30,000 chip designers working in the United States. The Semiconductor Industry Association estimates that 67,000 semiconductor jobs will go unfilled by 2030, or 22% of the projected workforce. Globally, Deloitte projects that 1 million additional skilled semiconductor workers will be needed by the end of the decade. The CHIPS Act is funding $52 billion in domestic semiconductor manufacturing. Intel, TSMC, and Samsung are building new fabs in Arizona, Ohio, and Texas. Every fab needs design engineers to create the chips those fabs will produce.

The talent pipeline cannot keep up. US universities graduate roughly 2,000 to 3,000 electrical engineering and computer engineering students with semiconductor-relevant skills per year. Many go into software, where starting salaries have historically been higher and the work more visible. The semiconductor industry is competing with Google, Meta, and every well-funded startup for the same engineering graduates who learned Verilog in college but could also write Python.

Compensation reflects this. FPGA engineers average $153,000 to $175,000 in the US, with senior FPGA engineers averaging $231,000 and reaching up to $285,000. ASIC design engineers average $150,000 to $163,000, but senior roles at NVIDIA, Apple, and Broadcom range from $193,000 to $504,000 in total compensation. VLSI engineers earn 30 to 80% more than the general engineering average. These numbers have climbed steadily since 2022 as AI chip demand and reshored semiconductor manufacturing compete for the same graduates.

The FPGA market is growing fast: $12.1 billion in 2024, projected to reach $25.8 billion by 2029. FPGAs are no longer niche components for telecom and military systems. They run inference accelerators, network packet processing, high-frequency trading systems, and prototyping platforms for every ASIC startup that cannot yet afford a tape-out. Engineers who can program these devices are now hired by industries that five years ago never thought about FPGAs.

The companies hiring HDL engineers span several categories. Established chipmakers: Intel, AMD, NVIDIA, Qualcomm, Broadcom, Marvell, Lattice Semiconductor. AI chip startups: Cerebras ($8.1 billion valuation), Groq (acquired by NVIDIA for $20 billion in December 2025), SambaNova, Tenstorrent ($3 billion-plus valuation). Defense and aerospace: BAE Systems, Lockheed Martin, Raytheon. And a growing number of companies that are not chip companies at all but need custom hardware: Microsoft (Azure FPGA accelerators), Amazon (Graviton, Trainium), Google (TPUs), and financial firms building low-latency trading infrastructure.

VHDL, Verilog, and SystemVerilog: what recruiters need to know

If you are sourcing HDL engineers for the first time, you need to understand the three languages and when each one matters. They are not interchangeable, and candidates will notice if you conflate them.

Verilog is the most widely used HDL for FPGA development and general RTL design. Its syntax resembles C, which makes it more accessible to software engineers who are learning hardware design. Verilog is the default choice for most FPGA projects, academic courses, and startups doing rapid prototyping. If a job posting says "Verilog" without further qualification, it usually means FPGA development or straightforward ASIC design.

VHDL is more verbose and strongly typed, with syntax derived from Ada. Where Verilog lets you get away with implicit type conversions and loose signal declarations, VHDL forces you to be explicit about every signal width, type conversion, and interface. This strictness is why VHDL dominates aerospace, defense, and European semiconductor companies. When a design error could cost millions (or lives), the compiler catching type mismatches before synthesis is worth the extra verbosity. If your company works with BAE Systems, Airbus, or any defense contractor, VHDL proficiency is likely a hard requirement.

SystemVerilog extends Verilog in two directions. For design, it adds structured data types, interfaces, and packages that make large SoC designs more manageable. For verification, it adds object-oriented programming: classes, constrained randomization, functional coverage, and assertions. The Universal Verification Methodology (UVM) is written in SystemVerilog and is the industry standard for verifying complex chips. A "SystemVerilog engineer" usually means a verification engineer, and verification engineers are arguably even harder to hire than RTL designers. Mid-level verification engineers at AI chip companies have been reported as hired within six hours of becoming available.

Most senior chip designers know at least two of the three. An engineer who has worked in both US commercial semiconductor and European defense will often be fluent in Verilog, VHDL, and SystemVerilog. That versatility is a strong signal, but it is not always necessary. Match the language requirement to the actual role: FPGA prototyping work needs Verilog, defense contracts need VHDL, and ASIC verification needs SystemVerilog.

Beyond the traditional HDLs, newer languages are gaining traction in the open-source hardware community. Chisel (a Scala-based HDL) is used by UC Berkeley's RISC-V projects and the CHIPS Alliance. Amaranth (formerly nMigen, Python-based) targets FPGA development with a more software-friendly workflow. SpinalHDL (also Scala-based) generates Verilog or VHDL from high-level descriptions. These tools lower the barrier to hardware design and attract engineers who might never have touched Verilog directly. Contributors to these projects often have strong software engineering backgrounds combined with genuine hardware design knowledge, a combination that is uncommon and worth paying attention to.

Where HDL engineers contribute on GitHub

Open-source hardware is where this gets interesting for recruiters. Five years ago, almost no chip design work happened in the open. Proprietary EDA tools, NDAs, and the sheer cost of tape-outs kept everything behind corporate firewalls. RISC-V changed that. The open instruction set architecture created an ecosystem where real processor designs, SoC platforms, and verification infrastructure are developed publicly on GitHub. The same seniority signals that work for software engineers apply here, but the repositories are different and the contributor communities are smaller.

RISC-V processor cores and SoCs. chipsalliance/chisel (4,600 stars) is the hardware construction language behind UC Berkeley's RISC-V processors, including the BOOM out-of-order core and Rocket core. Contributors to Chisel work at the intersection of programming language design and digital logic. riscv/riscv-isa-manual (4,600 stars) is the specification itself. Engineers who contribute to the ISA specification understand processor architecture at the deepest level. RISC-V International now has 4,600-plus members, up from 236 in 2019, and over 13 billion RISC-V cores have shipped.

Security-focused hardware. lowRISC/opentitan (3,300 stars) is an open-source silicon root of trust, backed by Google, lowRISC, and multiple semiconductor partners. OpenTitan is one of the few open-source projects that has gone through actual silicon tape-out. Contributors work on hardware security modules, cryptographic accelerators, and secure boot chains. This is production-grade chip design in the open, and the contributor list is a direct source of engineers who have shipped real silicon.

FPGA frameworks. enjoy-digital/litex (3,800 stars) is a Python-based SoC builder for FPGAs. LiteX lets engineers assemble complete systems-on-chip from modular components: CPU cores, memory controllers, Ethernet MACs, USB controllers. Contributors understand SoC architecture and the practical constraints of FPGA development. amaranth-lang/amaranth (2,000 stars) is a Python-based HDL that generates synthesizable Verilog. Amaranth contributors tend to be engineers who want the rigor of hardware design with the tooling ergonomics of software development.

Verification. cocotb/cocotb (2,300 stars) is a coroutine-based testbench framework that lets engineers write verification code in Python instead of SystemVerilog. This matters because it opens hardware verification to engineers with software backgrounds. Cocotb interfaces with commercial simulators (Synopsys VCS, Cadence Xcelium, Siemens Questa) and open-source ones (Icarus Verilog, Verilator). Contributors to cocotb understand both verification methodology and the Python ecosystem, which makes them effective bridges between hardware and software teams.

High-level synthesis and alternative HDLs. SpinalHDL/SpinalHDL (2,000 stars) generates VHDL and Verilog from Scala. It provides type safety, parameterization, and abstraction capabilities that raw Verilog and VHDL lack. The VexRiscv processor core, implemented in SpinalHDL, is one of the most widely used soft-core RISC-V implementations for FPGAs. Contributors to SpinalHDL are typically experienced hardware designers who hit the limits of traditional HDLs and built something better.

EDA tooling. The open-source EDA movement is smaller but growing. Projects like Yosys (open-source synthesis), nextpnr (open-source place-and-route), and Verilator (open-source Verilog simulator) let teams build chip design workflows without Synopsys, Cadence, or Siemens EDA licenses. Contributors to these tools understand the internals of synthesis and simulation, not just how to write HDL. That depth of knowledge is rare and directly useful for companies building custom EDA flows or optimizing their design toolchains.

Quality signals in hardware design code

Evaluating HDL code requires different criteria than evaluating software. A Verilog module that looks clean and well-structured might still fail timing, consume excessive area, or behave differently in simulation than on actual hardware. If you are a recruiter without a hardware background, these signals can help you assess contributions or talk more productively with hiring managers.

RTL design quality. Clean RTL (register-transfer level) code separates combinational logic from sequential logic clearly. Experienced designers use well-named signals, organize modules with clear input/output port lists, and parameterize designs for reuse. A module that hardcodes bus widths to 32 everywhere is less mature than one that uses parameters so the same module works for 8-bit, 16-bit, or 64-bit data paths. Look for designs that use generate statements and parameters rather than copy-pasting similar logic blocks. Sloppy RTL is easy to spot even without hardware expertise: inconsistent naming, missing comments on non-obvious timing decisions, monolithic modules that try to do too much.

Verification methodology. Writing the design is half the job. Proving it works is the other half, and verification typically consumes 60 to 70% of a chip project's engineering effort. Strong verification engineers write constrained-random testbenches that exercise corner cases a directed test would miss. They build coverage models that measure which design states have actually been tested. In SystemVerilog, look for UVM-based testbenches with proper agent/driver/monitor architecture. In Python-based flows, look for cocotb testbenches with assertions, coverage collection, and regression test organization. A developer who ships RTL with no testbench is not doing production-quality work.

Timing closure. "Meeting timing" means the design can operate at the target clock frequency after synthesis and place-and-route. This is the gap between hardware that works in simulation and hardware that works on a real chip. Experienced engineers think about timing from the start: they pipeline long combinational paths, register signals at module boundaries, and handle clock domain crossings with proper synchronizers. If you see a design with explicit pipeline stages, clock domain crossing modules, and comments referencing timing constraints, that engineer has shipped designs that actually run on hardware. These details are hard to fake.

Synthesis awareness. Not all valid HDL code synthesizes into efficient hardware. A software engineer might write a for-loop in Verilog expecting it to execute sequentially. It does not. It unrolls into parallel hardware. An experienced hardware designer knows which constructs synthesize well and which ones make the synthesis tool generate enormous, slow circuits. They avoid latches (usually a design mistake), use blocking and non-blocking assignments correctly, and understand the difference between simulation behavior and synthesis behavior. That knowledge takes years to build, which is why a "Verilog developer" with two months of experience is nothing like one with five years.

Documentation and architecture. Production chip designs include architecture documents, block diagrams, interface specifications, and register maps. On GitHub, look for README files that explain the design's architecture, interface protocols, and intended use cases. Designs that include timing diagrams, waveform references, or links to specification documents point to an engineer who thinks about communication and maintainability, not just functionality. When a single design error can cost a $10 million mask set, documentation discipline is a direct quality signal.

EDA tool proficiency. Synopsys (Design Compiler, VCS, Verdi), Cadence (Genus, Xcelium, Innovus), and Siemens EDA (Questa, Calibre) are the dominant commercial tool suites. Proficiency with these tools is often mandatory for interviews at semiconductor companies. On GitHub, you will not see proprietary EDA scripts, but you can see experience with open-source equivalents: Yosys for synthesis, Verilator for simulation, nextpnr for FPGA place-and-route, and KLayout for physical verification. An engineer who contributes to both HDL projects and EDA tool projects has an unusually complete understanding of the design flow.

The AI chip boom and what it means for hiring

The AI hardware market has made hiring HDL engineers much harder. US AI chip startups raised $5.1 billion in venture capital in the first half of 2025 alone. Groq's $20 billion acquisition by NVIDIA in December 2025 capped a decade of accelerating investment. Cerebras is valued at $8.1 billion. Tenstorrent has raised over $3 billion. SambaNova, Graphcore (acquired by SoftBank), d-Matrix, and dozens of smaller startups are all hiring from the same limited pool of chip designers.

These companies need the same engineers that Intel, AMD, and Qualcomm need. A senior ASIC design engineer who might have earned $200,000 total compensation at a traditional semiconductor company in 2020 can now command $350,000 to $500,000 at an AI chip startup with equity upside. Mid-level verification engineers are hired within hours of entering the market. AI chip companies move so fast that multi-week interview processes now lose candidates before they reach the offer stage.

What AI chip companies need from HDL engineers also differs from traditional semiconductor work. AI accelerators are defined by their data paths: matrix multiply units, activation function hardware, on-chip memory hierarchies optimized for tensor operations, and high-bandwidth interconnects. An engineer who designed a network switch ASIC or an LTE modem has strong fundamentals but may need to learn the architectural patterns specific to AI accelerators. Look for engineers who understand memory bandwidth optimization, systolic arrays, and dataflow architectures on top of standard RTL design skills.

FPGA engineers are especially sought after because FPGAs are the prototyping platform for AI chip startups before tape-out. A startup designing a custom AI accelerator will validate the architecture on an FPGA first, running real workloads and measuring performance before committing to a $10 million-plus ASIC fabrication. The engineer who does that FPGA prototyping needs to understand both the target ASIC architecture and the practical constraints of FPGA implementation: limited routing resources, block RAM architectures, DSP slice utilization, and the quirks of Xilinx (now AMD) or Intel (Altera) toolchains.

The defense sector compounds the problem. BAE Systems, Lockheed Martin, Raytheon, and Northrop Grumman all need FPGA and ASIC engineers for radar systems, electronic warfare, satellite communications, and missile guidance. These roles typically require US citizenship and security clearances, which further shrinks the candidate pool. Defense semiconductor work tends to use VHDL more heavily than commercial work, and the verification standards (DO-254 for airborne electronic hardware) are stricter than commercial flows. Engineers who have worked in defense bring discipline and thoroughness that transfers well to any safety-critical application.

How to search for HDL engineers on GitHub

GitHub is not the first place most semiconductor recruiters look for candidates. It should be. The open-source hardware community is still small compared to open-source software, so the signal-to-noise ratio is very high. An engineer who contributes Verilog or VHDL to GitHub projects is showing skills directly relevant to production chip design, and doing it publicly. The niche stack sourcing strategies we have covered apply here with some hardware-specific adjustments.

Language filter. GitHub recognizes Verilog, VHDL, and SystemVerilog as distinct languages. Filter repositories or code search by language:verilog, language:vhdl, or language:systemverilog to surface hardware projects. You can also search for language:chisel or language:scala in repositories with hardware-related names to find Chisel-based designs. The total number of results will be much smaller than a search for Python or JavaScript. That is the point. Nearly everyone who shows up is a real hardware engineer.

RISC-V ecosystem. RISC-V International has 4,600-plus member organizations. The contributor lists of major RISC-V projects (Rocket Chip, BOOM, OpenTitan, VexRiscv, CVA6) are essentially curated rosters of engineers working on open processor design. Many of them work at semiconductor companies and contribute to open-source RISC-V projects as part of their professional work. An engineer who contributes to OpenTitan is likely working on a Google-backed silicon project; one who contributes to BOOM may be at UC Berkeley, SiFive, or a RISC-V startup.

CHIPS Alliance and FOSSi Foundation. The CHIPS Alliance (Linux Foundation) and the Free and Open Source Silicon Foundation coordinate most of the open-source hardware activity on GitHub. Their project lists are directories of active hardware design work. The FOSSi Foundation also organizes ORConf and Latch-Up conferences, and those speaker lists are another sourcing channel.

Contribution type matters more than volume. A chip designer might make 10 commits per month to a single RISC-V core, while a web developer makes 100 commits across multiple projects. Hardware design has longer iteration cycles: a single RTL change might require hours of simulation, synthesis, and timing analysis before it can be committed. Low commit frequency does not mean low activity. Look at the substance of contributions: RTL module additions, testbench development, timing constraint files, and synthesis scripts are high-value work even when they appear infrequently.

Academic connections. Much of the open-source hardware work on GitHub comes from university research groups. UC Berkeley (RISC-V, Chisel, BOOM), ETH Zurich (PULP Platform, CVA6), IIT Madras (SHAKTI processors), and MIT (various FPGA projects) all have active GitHub organizations. Graduate students and postdocs who contribute to these projects are potential hires, and their advisors and lab alumni networks are referral sources. Academic contributors tend to have deep theoretical knowledge and may need mentoring on production design flows, but their architectural thinking and verification skills are often strong.

Cross-referencing with LinkedIn and conferences. Many HDL engineers on GitHub list their employer and role on their profile or in commit metadata. Cross-referencing GitHub contributors with LinkedIn profiles and conference speaker lists (DAC, ICCAD, FPGA Conference, RISC-V Summit) fills out the picture. An engineer who presented a paper at DAC and contributes to OpenTitan is at a different level than one with a few tutorial-level Verilog repositories.

A practical HDL sourcing workflow

If you are Elena, a recruiter who has sourced scientific computing talent but never hired chip designers, this workflow maps what you already know about technical sourcing onto the hardware domain.

Step 1: Classify the role. HDL engineering is not one job. The major specializations are RTL design (writing the logic), verification (proving it works), physical design (layout and timing closure), and FPGA implementation (mapping designs to specific FPGA devices). Each requires different skills, different tools, and different GitHub signals. An RTL designer and a verification engineer both write SystemVerilog, but the code they produce looks completely different. Get specific about which role you are filling before you start sourcing.

Step 2: Map the language to the domain. Verilog for FPGA work and commercial ASIC design. VHDL for defense, aerospace, and European companies. SystemVerilog for ASIC verification and complex SoC design. Chisel or SpinalHDL for RISC-V and open-source processor development. Cocotb (Python) for software-friendly verification flows. The language narrows your search fast, and using the wrong one in a job posting or outreach message tells the candidate you do not understand the role.

Step 3: Identify target repositories. For RISC-V processor design: chipsalliance/chisel, lowRISC/opentitan, chipsalliance/rocket-chip. For FPGA SoC development: enjoy-digital/litex, amaranth-lang/amaranth. For verification: cocotb/cocotb. For high-level synthesis: SpinalHDL/SpinalHDL. For EDA tooling: YosysHQ/yosys, verilator/verilator. For specific FPGA targets: projects built on Xilinx/AMD or Intel/Altera development boards. Map your technical requirements to the repositories where relevant work happens.

Step 4: Extract and evaluate contributors. Pull recent contributors from target repositories. For hardware projects, extend the recency window to 6 to 12 months rather than the 3 to 6 months typical for software, because hardware design cycles are longer. Evaluate contributions for the quality signals described above: clean RTL structure, verification methodology, parameterized designs, and architecture documentation. An engineer who contributed a complete UART controller with testbench, timing constraints, and synthesis results has shown production-relevant skills. General seniority signals like code review participation and architectural decision-making apply here too.

Step 5: Check for industry experience. Open-source hardware contributors often work at semiconductor companies during the day. Check their GitHub profile, LinkedIn, and any published papers. An engineer who works at SiFive and contributes to RISC-V projects on GitHub is applying commercial experience to their open-source work. An engineer at Lattice Semiconductor who has personal FPGA projects on GitHub is building beyond their day job. Both are strong signals, but they mean different things depending on the role you are filling.

Step 6: Consider adjacent backgrounds. The talent shortage means you may need to look beyond pure HDL engineers. Embedded systems engineers who work at the hardware-software boundary often have FPGA experience. Digital signal processing engineers frequently implement algorithms in Verilog or VHDL. Computer architecture researchers understand processor design even if they have not taped out a chip. Software engineers who contribute to cocotb or Chisel are actively moving into hardware. Do not dismiss candidates from adjacent fields if they show genuine hardware design engagement on GitHub.

Step 7: Write outreach that shows you understand the work. Generic recruiter messages fail harder with hardware engineers than with most developers. These engineers are used to hearing from recruiters who cannot tell VHDL from Verilog, who confuse FPGA programming with embedded C, or who think "hardware engineer" means someone who assembles computers. Reference specific contributions: "I saw your AXI4 interconnect implementation in LiteX and the way you handled arbitration for multiple masters. We are building a custom AI inference accelerator and need someone who understands on-chip bus architectures at that level." That kind of specificity gets responses. "I found your profile and you seem like a great fit for our hardware team" does not.

Step 8: Scale with tooling. The manual workflow works but hits limits quickly in a small community. Tools like riem.ai analyze GitHub event data across 30 million-plus events per month, including Verilog, VHDL, and SystemVerilog repositories. Instead of manually browsing contributor graphs on RISC-V projects, you can search by natural language ("FPGA engineers who have contributed to RISC-V cores or worked with Xilinx toolchains") and get ranked candidates with contribution summaries and quality assessments. In a talent pool this small, efficient discovery matters. Every qualified candidate you miss is likely being contacted by three other companies already.

Frequently asked questions

How many VHDL and Verilog engineers are there?

Roughly 20,000 to 30,000 chip designers work in the United States; the global total is much higher when you include Taiwan, South Korea, Japan, Germany, and Israel. The Semiconductor Industry Association estimates 67,000 semiconductor jobs in the US will go unfilled by 2030, or 22% of the industry's projected workforce. Deloitte projects 1 million additional skilled semiconductor workers will be needed globally by 2030. These numbers span RTL designers, verification engineers, physical design engineers, and related roles, but HDL proficiency is a baseline requirement for most of them.

What salary should I expect to pay FPGA and ASIC engineers?

FPGA engineers average $153,000 to $175,000 in the US, with senior FPGA engineers averaging $231,000 and reaching up to $285,000 at top companies. ASIC design engineers average $150,000 to $163,000, but senior roles at NVIDIA, Apple, and Broadcom range from $193,000 to $504,000 total compensation. VLSI engineers earn 30 to 80 percent more than the general engineering average. AI chip startups are pushing compensation even higher with equity packages that reflect multi-billion-dollar valuations.

What is the difference between VHDL, Verilog, and SystemVerilog?

Verilog is the most common HDL for FPGA development and general RTL design. Its syntax resembles C, making it accessible to software engineers. VHDL is more verbose and strongly typed, with syntax derived from Ada. It dominates aerospace, defense, and European semiconductor companies due to its stricter type checking and deterministic simulation semantics. SystemVerilog extends Verilog with object-oriented verification features (classes, constrained randomization, coverage groups) and is the standard for modern ASIC verification using UVM methodology. Most senior chip designers know at least two of the three.

Can software engineers transition to HDL and chip design roles?

Partially, but the transition is harder than moving between software languages. HDL code describes physical hardware that runs in parallel, not sequential instructions. Concepts like clock domains, timing constraints, metastability, and synthesis optimization have no software equivalent. Software engineers who learn Chisel (Scala-based HDL) or Amaranth (Python-based HDL) can contribute to digital design, and verification engineering using cocotb (Python-based testbenches) is the most accessible entry point. But RTL design for production ASICs requires understanding of semiconductor physics, fabrication constraints, and EDA tool flows that take years to develop.

What HDL projects should I look for on GitHub?

For RISC-V and processor design: chipsalliance/chisel, riscv/riscv-isa-manual, lowRISC/opentitan. For FPGA frameworks: enjoy-digital/litex, amaranth-lang/amaranth. For verification: cocotb/cocotb. For high-level synthesis: SpinalHDL/SpinalHDL. Contributors to these projects are working on open-source chip design infrastructure. The CHIPS Alliance and RISC-V International ecosystems are where most open-source hardware activity concentrates.

How long does it take to hire an HDL engineer?

Sixty to 120 days is typical, and specialized roles can take longer. Mid-level verification engineers at AI chip companies have been reported as hired within 6 hours of entering the market. The shortage is structural: university programs cannot produce graduates fast enough for both established chipmakers and the wave of AI chip startups. Defense and aerospace roles add security clearance timelines on top of the already long hiring cycle. Sourcing from open-source hardware communities on GitHub can shorten time-to-fill by reaching engineers who are building in the open but not actively job hunting.